Recently, flat-panel displays such as a liquid-crystal display have become widely spread in the world, and many of these are said to be those of an active matrix type. The display unit of a liquid crystal device that uses an active matrix driving method is constituted from a structure including a semiconductor substrate with transparent pixel electrodes and thin film transistors (TFTs) disposed thereon, an opposing substrate with one transparent electrode formed on an entire surface thereof, and a liquid crystal sealed between these two opposing substrates. Then, by controlling the TFTs each having a switching function, a predetermined voltage is applied to each pixel electrode, the transmissivity of the liquid crystal is changed by a potential difference between each pixel electrode and the electrode on the opposing substrate, and the liquid crystal having a capacitive property holds its potential difference and its transmissivity for a predetermined period. An image is thereby displayed.
On the semiconductor substrate, data lines for sending a plurality of level voltages (gray-scale voltages) applied to the pixel electrodes and scanning lines each for sending a TFT switching control signal are wired in a lattice form. The data lines have become capacitive loads caused by the capacitance of the liquid crystal sandwiched between the electrode of the opposing substrate and the data lines and capacitances generated at intersections with the respective scanning lines.
Application of a gray-scale voltage to each pixel electrode is carried out through a data line, and supplying of the gray-scale voltage is performed to all pixels connected to the data line within one frame period (of approximately 1/60 seconds). For this reason, a data line driving circuit for driving the data line must drive the data line that is the capacitive load with high voltage accuracy and at high speed.
Then, for application to portable devices, low power consumption is further demanded for the data driving circuit, in addition to the driving of the data line with high accuracy and at high speed.
Further, it is required that the data line driving circuit perform driving of a lot of data lines with exact gray-scale voltages without offset. That is, high output voltage accuracy is required for an output amplifier circuit used in the data line driving circuit.
FIGS. 13 and 14 are diagrams respectively showing an example of a configuration of a conventional amplifier circuit that aims at high accuracy and its timing operation (refer to Patent Document 1 that will be hereinafter described).
FIG. 13 is a diagram showing a configuration of an offset canceling amplifier having a function of reducing an output offset caused by a variation in transistor devices constituting an amplifier circuit. Referring to FIG. 13, this circuit has NMOS transistors M3 and M4 constituting a differential pair with the commonly connected source thereof connected to one terminal of a constant current source M8 and NMOS transistors M5 and M6 constituting a differential pair with the commonly connected source thereof connected to one terminal of a constant current source M9. The drains of the NMOS transistors M3 and M5 are connected to the drain of a PMOS transistor M1. The drains of the NMOS transistor M4 and an NMOS transistor M6 are connected to the connecting point between the drain and the gate of the PMOS transistor M2. The sources of the PMOS transistor M1 and a PMOS transistor M2 are connected to a high-potential power supply VDD, and the gates of the PMOS transistor M1 and the PMOS transistor M2 are connected in common. The PMOS transistors M1 and M2 constitute a current mirror that constitutes a common active load for the differential pairs (M3, M4) and (M5, M6). The connecting node between the NMOS transistor M5 and the PMOS transistor M1 is connected to the gate of a PMOS transistor M7 with the source thereof connected to the power supply VDD and the drain thereof connected to an output terminal 2. Between the output terminal 2 and a low-potential power supply VSS, a current source M10 is connected. The gates of the NMOS transistors M3 and M5 are connected to an input terminal 1, and the gate of the NMOS transistor M6 is connected to the input terminal 1 through a switch SW1, and connected to the output terminal 2 through a switch SW2. The gate of the NMOS transistor M4 is connected to the other terminal of a capacitance C1 with one terminal thereof connected to the low-potential power supply VSS. A switch SW3 is connected between the gate of the NMOS transistor M4 and the output terminal 2.
Referring to the timing chart in FIG. 14, in the amplifier circuit shown in FIG. 13, the switches SW1 and SW3 are turned on, and the switch SW2 is turned off during a period t1 of one data output period. To the input pair of the differential pair (M3, M4), an input voltage Vin and an output voltage Vout are input, and the input voltage Vin is input in common to the input pair of the differential pair (M5, M6). At this point, the output voltage Vout becomes a voltage (Vin+Vf) including an offset voltage (ΔV=Vf; the offset voltage output when the same voltage is applied to the input pair of a differential pair), and this voltage is stored in the capacitance element C1.
Then, the switches SW1 and SW3 are turned off, and the switch SW2 is turned on during the period t2. As a result, to the input pair of the differential pair (M3, M4), the input voltage Vin and the terminal voltage (Vin+Vf) of the capacitance element C1 are differentially input. To the input pair of the differential pair (M5, M6), the input voltage Vin and the output voltage Vout are differentially input. At this point, the voltage that is the same as that during the period t1 is input to the input pair of the differential pair (M3, M4), and the differential pair (M5, M6) also operates so as to maintain the same state in the period t1.
Accordingly, the output voltage Vout in the period t2 becomes the voltage equal to the input voltage Vin and becomes stable. That is, the circuit shown in FIG. 13 cancels an output offset and can amplify the voltage that is equal to the input voltage, for output.
A configuration shown in FIG. 15 is a modification of the circuit shown in FIG. 13 (refer to Patent Document 2 which will be described later). The configuration shown in FIG. 15 is different from the configuration in FIG. 13 in that while in the configuration of the circuit shown in FIG. 13, the input voltage Vin is input to the gate of the transistor M3 that constitutes the differential pair, a reference voltage Vref is input to the gate of the transistor M3 that constitutes the differential pair in the example in FIG. 15. Incidentally, a timing chart for controlling respective switches in FIG. 15 is the same as that shown in FIG. 14.
In the amplifier circuit shown in FIG. 15, the switches SW1 and SW3 are turned on, and the switch SW2 is turned off during the period t1 of the one data output period. The input voltage Vin and the reference voltage Vref are input to the input pair of the differential pair (M3, M4), and the Vin is input to the input pair of the differential pair (M5, M6). At this point, the output voltage Vout becomes a voltage (Vref+Vf) that adds the offset voltage Vf to the reference voltage Vref, and this voltage is applied to one terminal of the capacitance element C1. Then, during the period t2, the switches SW1 and SW3 are turned off, and the switch SW2 is turned on. Then, the input voltage Vref and the voltage (Vref+Vf) at the terminal of the capacitance element C1 are input to the input pair of the differential pair (M3, M4), and the Vin and the output voltage Vout are input to the input pair of the differential pair (M5, M6). At this point, the voltages which are the same as that in the period t1 are input to the input pair of the differential pair (M3, M4), and the differential pair (M5, M6) also operates to maintain the state that is the same as in the period t1. Accordingly, the output voltage Vout in the period t2 becomes equal to the input voltage Vin and becomes stable. That is, the circuit shown in FIG. 15 can cancel an output offset and can amplify the voltage that is equal to the input voltage, for output.
If the reference voltage Vref is set to an intermediate voltage in an output voltage range, the amount of the potential variation of the output voltage Vout in the period t1 can be reduced more than in the configuration in FIG. 13. For this reason, the period t1 can be reduced, and the period t2 during which highly accurate driving is performed can be extended.
[Patent Document 1]
JP Patent Kokai JP-A-2001-292041 (pp. 3-4, FIG. 1)
[Patent Document 2]
JP Patent Kokai JP-A-2003-168936 (pp. 3-4, FIG. 1)